Flip chip package relates to a chip scale package and makes mounting a chip on a circuit board or other electric interface very convenient by using one surface of the chip. For a trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor), gate, source and drain metals for external connection should be placed on one surface of the trench MOSFET, and can be bonded with solder balls on their surfaces for flip chip packaging. Trench MOSFET having a top side drain can be integrated with integrated circuit for some applications and for package foot print reduction.
Please refer to FIG. 1A for a prior art U.S. Pat. No. 7,352,036 which disclosed an N-channel trench MOSFET 100 having a top side drain by using a deep sinker trench 101 filled with a conductive material 102 and extending from a top surface of an n− epitaxial layer 103 down to an n+ substrate 104. A dielectric layer 105 only lining the sinker trench 101 sidewalls insulates the conductive material 102 from the n− epitaxial layer 103. However, the process to form the deep sinker trench 101 and the conductive material 102 is complicated and not cost effective. Firstly, the deep sinker trench 101 is formed with an additional mask; secondly, forming the deep sinker trench 101 needs extra deep dry silicon etch; thirdly, an additional oxide etch is needed to remove the dielectric layer 105 from trench bottom of the deep sinker trench 101. FIG. 1B shows a P-channel trench MOSFET 110 having a top side drain according to another prior art U.S. Pat. No. 6,653,740. In FIG. 1B, a P+ substrate 111 is used and a P epitaxial layer 112 is grown atop the P+ substrate 111. A drain metal 113 is shown as contacting an upwardly extending portion of the P+ substrate 111. The trench MOSFET 110 is also formed through a complicated and not cost effective process. Firstly, a deep and wide trench 114 is etched into the P+ substrate 111 to form an active area; secondly, the P epitaxial layer 112 is formed and additional CMP (Chemical Mechanical Polishing) is required to remove excess epitaxial layer from the P+ substrate 111. According to the same prior art U.S. Pat. No. 6,653,740, another P-channel trench MOSFET 120 having bidirectional structure is shown in FIG. 1C, which has a high on-resistance suffered from additional channel resistance and drift region resistance.
Therefore, there is still a need in the art of the semiconductor power device, particularly for trench MOSFET design and fabrication, to provide a novel cell structure, device configuration and fabrication process that would resolve these difficulties and reduce the manufacturing cost.